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74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear
October 1996 Revised March 1999
74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear
General Description
The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs (J, K, PRESET, CLEAR, and CLOCK) and outputs (Q, Q). These devices are edge sensitive and change states synchronously on the negative going transition of the clock pulse. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. Clear and Preset are independent of the clock and are accomplished by a low logic level on the corresponding input. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.
Features
s Input voltage level translation from 5V-3V s Ideal for low power/low noise 3.3V applications
Ordering Code:
Order Number 74LVX112M 74LVX112SJ 74LVX112MTC Package Number M16A M16D MTC16 Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names J1, J2, K1, K2 CLK1, CLK2 CLR1, CLR2 PR1, PR2 Q1, Q2, Q1, Q2 Data Inputs Clock Pulse Inputs (Active Falling edge) Direct Clear Inputs (Active LOW) Direct Preset Inputs (Active LOW) Description
(c) 1999 Fairchild Semiconductor Corporation
DS012158.prf
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74LVX112
Truth Table
Inputs PR L H L H H H H CLR H L L H H H H CP X X J X X X h l h l K X X X h h l l Outputs Q H L H Q0 L H Q0 Q L H H Q0 H L Q0
H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial = HIGH-to-LOW Clock Transition Q0 (Q0) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.

X
Logic Diagram
(One Half Shown)
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74LVX112
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) Power Dissipation 50 mA -65C to +150C 180 mW 25 mA -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA -0.5V to 7V -0.5V to +7.0V
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Input Rise and Fall Time (t/v) 2.0V to 3.6V 0V to 5.5V 0V to VCC -40C to +85C 0 ns/V to 100 ns/V
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage VIL LOW Level Input Voltage VOH HIGH Level Output Voltage VOL Low Level Output Voltage IIN ICC Input Leakage Current Quiescent Supply Current VCC 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.0 2.0 3.0 3.0 3.6 3.6 1.9 2.9 2.58 0.0 0.0 0.1 0.1 0.36 0.1 2.0 2.0 3.0 TA = +25C Min 1.5 2.0 2.4 0.5 0.8 0.8 1.9 2.9 2.48 0.1 0.1 0.44 1.0 20.0 A A V VIN = VIL or VIH V Typ Max TA = -40C to +85C Min 1.5 2.0 2.4 0.5 0.8 0.8 VIN = VIL or VIH IOH = -50 A IOH = -50 A IOH = -4 mA IOL = 50 A IOL = 50 A IOL = 4 mA VIN = 5.5V or GND VIN = VCC or GND V V Max Units Conditions
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74LVX112
AC Electrical Characteristics
Symbol tPLH tPHL Parameter Propagation Delay CPn to Qn or Qn 3.3 0.3 tPLH tPHL Propagation Delay PR or CLR to Qn or Qn 3.3 0.3 tW tS tH tREC fMAX Pulse Width (CP or CLR or PR) Setup Time (Jn or Kn to CPn) Hold Time (Jn or Kn to CPn) Recovery Time (CLR or PR to CP) Maximum Clock Frequency 3.3 0.3 tOSLH, tOSHL Output to Output Skew (Note 3) 2.7 3.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 5.0 5.0 5.5 5.0 1.0 1.0 6.5 6.0 90 85 110 90 140 115 150 120 1.5 1.5 2.7 VCC (V) 2.7 TA = +25C Min Typ 7.5 11.0 8.5 10.0 7.0 10.1 6.7 9.7 Max 12.0 16.7 11.0 15.0 11.5 14.3 10.2 13.5 TA = -40C to +85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 5.0 5.5 5.0 1.0 1.0 6.5 6.0 85 70 100 80 1.5 1.5 ns MHz Max 14.2 19.0 13.4 16.5 12.3 16.5 11.7 15.0 ns ns ns ns 15 50 15 50 50 ns ns Units CL (pF) 15 50 15 50 15 50 15 50
Note 3: Parameter guaranteed by design. tOSLH = |tPLHm-tPLHn|, tOSLH = |tPHLm-tPHLn|
Capacitance
Symbol CIN CPD Input Capacitance Power Dissipation Capacitance (Note 4)
Note 4: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Parameter Min
TA = +25C Typ 4 18 Max 10
TA = -40C to +85C Min Max 10
Units pF pF
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74LVX112
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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